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| - | ====== Photos ====== | ||
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| - | ** Some pics of the project ** | ||
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| - | ===== Version 1 - veroboard ===== | ||
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| - | <WRAP group> | ||
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| - | <WRAP third column> | ||
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| - | Mark 1 in all its glory | ||
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| - | Twin LCD displays. 2-line for RTC and Uptime. 4 Line for monitor. | ||
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| - | <WRAP third column> | ||
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| - | RTC Chip and 2 debounced push buttons on the top breadboard. RTC is fed with 32.768kHz from a function generator | ||
| - | awaiting for a new xtal. | ||
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| - | 4-input AND gate for VIA IRQ connection to CPU on the other breadboard. | ||
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| - | I/O board with 2 65C22 VIAs. Beeper piezo sounder in the Altoids tin. | ||
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| - | <WRAP third column> | ||
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| - | ===== Version 2 ===== | ||
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| - | * Planned to be built using Wirewrap methods but seems to have been forgotten about | ||
| - | * I'll possibly return to the project in winter 2024/5? | ||
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| - | --- //John Pumford-Green 29/09/22 08:21// | ||
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| - | ===== Further Information ===== | ||
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| - | {{tag>}} | ||
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